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Why VLSI

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Published in: Networking
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About VLSI

Najeemullah B / Hyderabad

8 years of teaching experience

Qualification: M.Tech (Moguls Institute of learning - 2007)

Teaches: Algebra, Computer Science, Mathematics, Physics, B.Tech Tuition, Electronics, M.Tech Tuition, Railways Exams, RRB, Sub-Inspector Exam, UGC Exams, Chemical, Electrical, Embedded Systems, Hardware Training, Informatica, MCA Subjects

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  1. why VLSI? Moore's Law. The VLSI design process. o IP-based design.
  2. Why VLSI? o Integration improves the design: t' lower parasitics = higher speed; o lower power; physically smaller, o Integration reduces manufacturing cost-(almost) no manual assembly,
  3. VLSI and you Microprocessors: personal computers; microcontrollers. DRAM/SRAM, Special-purpose processors,
  4. Moore's Law Gordon Moore: co-founder of Intel, Predicted that number of transistors per chip would grow exponentially (double every 18 months), Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles,
  5. Moore's Law plot 108 107 106 103 1960 integrated circuit invented 1970 1980 1990 e memory CAJ 2000 2010 year
  6. Moore's Law and Intel processors # transistors/year 700000000 600000000 500000000 400000000 300000000 —# transistors 200000000 100000000
  7. Moore/ Intel log scale Log(# transistors)/year 10 9 8 7 6 5 —Senes I 4 3 2 1 1982 1985 1989 1993 1995 1997 1999 2000 2001 2003 2004
  8. Terminology Manufacturing node: technology at a particular channel length, Deep submicron technology: 250-100 nm, Nanometer technology: 1 00 nm and below,
  9. The cost of fabrication Current cost: $4 billion, Typical fab line occupies about 1 city block, employs a few hundred people, Most profitable period is first 18 months-2 years,
  10. Cost factors in ICs For large-volume ICs: packaging is largest cost; O testing is second-largest cost. For low-volume ICs, design costs may swamp all manufacturing costs,
  11. Cost of design Design cost can be significant: $20 million for a large ASIC, $500 million for a large CPU, Cost elements: Architects, logic designers, etc. CAD tools. Computers the CAD tools run on,
  12. Intellectual property o Intellectual property (IP): pre-designed components, May come from outside vendors, internal SOUrces. o IP saves time, design cost, o IP blocks must be designed to be reused,
  13. Reliability Nanometer technologies require attention to reliability, Design-for-manufacturing (DEM) and design-for- yield (DFY) techniques adjust the design to improve yield, Circuit and architecture techniques can compensate for unreliable components,
  14. The VLSI design process May be part of larger product design, Major levels of abstraction: O specification; architecture; O logic design; D circuit design; O layout,
  15. Challenges in VLSI design Multiple levels of abstraction: transistors to CPUs, Multiple and conflicting constraints: low cost and high performance are often at odds, Short design time: Late products are often irrelevant,
  16. Dealing with complexity Divide-and-conquer: limit the number of components you deal with at any one time, Group several components into larger components: D transistors form gates; gates form functional units; O functional units form processing elements; etc,
  17. Hierarchical name o Interior view of a component: D components and wires that make it up. Exterior view of a component — type: o body; pins, b cout sum Full adder cin
  18. Instantiating component types Each instance has its own name: D addl (type full adder) o add2 (type full adder), Each instance is a separate copy of the type: cout Add .a Addl.a sum a Addl(Fu11 adder) b cin sum a Add2(Fu11 adder) b cin
  19. A hierarchical logic design boxl z box2 x
  20. Net lists and component lists Net list: netl : top.inl inl ein net2: il .0Ut xxx.B topinl : top,nl xxx,xinl topin2: top.n2 xxx,xin2 botinl : top,n3 xxx,xin3 net3: XXX,OUt i2.in outnet: i2.out top.out Component list: top: inl =netl n 1 =topinl n2=topin2 n3=topine out=outnet i 1: in=netl out=net2 x x x: xinl =topinl xin2=topin2 xin3=botin1 B=net2 out=net3 i2: in=net3 out=outnet
  21. Component hierarchy top xxx
  22. Hierarchical names Typical hierarchical name: D top/ il .foo component pin
  23. Layout and its abstractions Layout for dynamic latch:
  24. Stick diagram
  25. Transistor schematic
  26. Mixed schematic 6 inverter
  27. Levels of abstraction Specification: function, cost, etc, Architecture: large blocks, Logic: gates + registers, Circuits: transistor sizes for speed, power, Layout: determines parasitics,
  28. Circuit abstraction ContinUOUS voltages and time:
  29. Digital abstraction Discrete discrete time: sum full sum ad&r full sum cin
  30. Register-transfer abstraction Abstract components, abstract data types: 0010 0001 0100 0011
  31. Top-down vs, bottom-up design Top-down design adds functional detail, Create lower levels of abstraction from upper levels. Bottom-up design creates abstractions from low- level behavior. Good design needs both top-down and bottom-up efforts,
  32. Design abstractions function English Executable program Sequential machines Logic gates transistors rectangles specification behavior register- ansf logic circuit layout Throughput, design time Function units, clock cycles Literals, logic depth nanoseconds microns cost
  33. Design validation Must check at every step that errors haven't been introduced-the longer an error remains, the more expensive it becomes to it, Forward checking: compare results of less- and more-abstract stages, Back annotation: copy performance numbers to earlier stages,
  34. Manufacturing test Not the same as design validation: just because the design is right doesn't mean that every chip coming off the line will be right, Must quickly check whether manufacturing defects destroy function of chip, Must also speed-grade,
  35. IP-based design Almost every chip Uses some form of IP: Standard cell libraries. Memories, D IP blocks, Designers must know how to: Create IPO o Use I p,
  36. Types of IP Hard IP: D Pre-designed layout, Allows more detailed characterization. Soft IP: No layout---logic synthesis, etc. D IP layout is created by the IP user.
  37. Hard IP Must conform to many standards: D Layout pin placement. O Layer usage, Transistor sizing, Hard IP blocks are usually qualified on a particular process, Component is fabricated and tested to show that the IP works on that fab line,
  38. Soft IP Conformance of layout to local standards is easier since it is created by the user, Timing can only be estimated until the layout is done, Must conform to interface standards, A wrapper adapts a block to a new interface.
  39. IP across the design hierarchy Standard cells, O Pitch matched in rows, compatible drive, Register-transfer modules, Memories, CPUs, Busses, Cl I/o devices,
  40. Specifying IP Hard or soft? Functionality, Performance, including process corners, Power consumption, Special process features required,
  41. The lifecycle extraction database spec HDL design validation qualification modules documentation docs chip design
  42. Using IP May come from vendor, open source, or internal group, Must identify candidate IP, evaluate for suitability, May have to pay for IPO May want to qualify IP before use, particularly if it pushes analog characteristics,

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