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IC Fabrication

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Published in: Networking
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Fabrication of Integrated Circuits

Najeemullah B / Hyderabad

8 years of teaching experience

Qualification: M.Tech (Moguls Institute of learning - 2007)

Teaches: Algebra, Computer Science, Mathematics, Physics, B.Tech Tuition, Electronics, M.Tech Tuition, Railways Exams, RRB, Sub-Inspector Exam, UGC Exams, Chemical, Electrical, Embedded Systems, Hardware Training, Informatica, MCA Subjects

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  1. Topics Basic fabrication steps. Transistor structures. Basic transistor behavior. Latch up.
  2. Our technology We will study a generic 1 80 nm technology. Assume 1 . 2 V supply voltage. Parameters are typical values. Parameter sets/ Spice models are often available for 1 80 nm, harder to find for 90 nm.
  3. Fabrication services Educational services: U.S.: MOS'S EC: EuroPractice Taiwan: ac Japan: VDEC Foundry = fabrication line for hire. Foundries are major source of fab capacity today.
  4. Fabrication processes IC built on silicon substrate: some structures diffused into substrate; other structures built on top of substrate. Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped) Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal). Silicon dioxide (Si02) is insulator.
  5. Simple cross section Si02 tra sistor meta13 meta12 metal 1 via poly substrate
  6. Photolithography Mask patterns are put on wafer using photo- sensitive material:
  7. Process steps First place tubs to provide properly-doped substrate for n-type, p-type transistors: p-tub substrate p-tub
  8. Process steps, cont'd. Pattern polysilicon before diffusion regions: poly p-tub gate oxide poly p-tub
  9. Process steps, cont'd Add diffusions, performing self-masking: poly poly p-tub
  10. Process steps, cont'd Start adding metal layers: metal I p-tub metal I vias
  11. Transistor structure n-type transistor: w 502 poly source (n+) channel substrate (p) drain (n+)
  12. 0.25 micron transistor (Bell Labs) gate oxide source/drain silicide poly
  13. Transistor layout n-type (tubs may vary):
  14. Drain current characteristics vs = 1.2V linear sturation vs = o.9V vs = 0.7\/ DS
  15. Drain current Linear region (Vds < v g s Saturation region (Vds > 0.5k' (W/ - Vt) 2 5 Vds2) vgs - vt):
  16. 1 80 nm transconductances Typical values: n-type: 1 70 kn' vtn = 0.5 V p-type: 30 PIA/\/2 k vtPp= -0.5 V
  17. Current through a transistor Use 180 nm parameters. Let W/ L = 3/2. Measure at boundary between linear and saturation regions. - 5.3 - 62
  18. Basic transistor parasitics Gate to substrate, also gate to source/drain. Source/drain capacitance, resistance. cgd drain source overlap
  19. Basic transistor parasitics, cont'd Gate capacitance Cg. Determined by active area. Source/drain overlap capacitances Cgs, C Determined by source/gate and drain/gate overlaps. Independent of transistor L. c - col W Gate/ bulk overlap capacitance.
  20. Latch-up CMOS ICs have parastic silicon-controlled rectifiers (SCRs). When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip. Early CMOS problem. Can be solved with proper circuit/ layout structures.
  21. Parasitic SCR circuit on off I-V behavior
  22. Parasitic SCR structure p-tub n-tub
  23. Solution to latch-up Use tub ties to connect tub to power rail. Use enough to create low-voltage connection. metal 1 (VDD) oxide n+ n-tub substrate
  24. Tub tie layout metal (VDD) P-tub

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