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CMOS OPAMP

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Published in: Networking
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Design of  CMOS OPAMP

Najeemullah B / Hyderabad

8 years of teaching experience

Qualification: M.Tech (Moguls Institute of learning - 2007)

Teaches: Algebra, Computer Science, Mathematics, Physics, B.Tech Tuition, Electronics, M.Tech Tuition, Railways Exams, RRB, Sub-Inspector Exam, UGC Exams, Chemical, Electrical, Embedded Systems, Hardware Training, Informatica, MCA Subjects

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  1. CMOS Op-amp
  2. Two-stage CMOS Op-amp The two stage CMOS op-amp has performance very close to the modern designs. ' It has two gain stages with first stage as differential-input single-ended output and the second stage as a common- source gain stage. ' Capacitor Cc is included to ensure stability when the op- amp is used with feedback.
  3. Circuit Diagram 10 14 12 Bias circuitry Differential-input first stage 16 Common-source second stage Output buffer Fig. Op-amp circuit diagram
  4. Input Specifications of op-amp The two stage op-amp is designed with the following specifications to meet the requirements of pipeline ADC. Op-amp gain = 10000 V/v Unity-gain frequency = 50 Mhz Slew rate = 100 V/us Compensation capacitor(Cc) = 1 pf
  5. Op-amp Gain The gain of first stage can be derived as Avl= gmlfrds2// rds4 ) and gml= (9 1 (Ibias1)/2 2•upCox The second stage is simply a common-source gain stage with a p-channel active load,Q6. -gm7frds6/frds7)
  6. The gain in the first stage is given by outl sc For the overall gain, we have Ads) The unity gain frequency, wta, Ota — -gmlZouit sccA2 cut gml gml
  7. Slew rate ' Slew rate is an important high frequency parameter of an op-amp and can be defined as maximum rate at which output changes when input signals are large. SR= (dvout/dt) I max= (I Since ID5- 2 IDI, 21D1/cc )/Cc = ID5/Cc Cc max
  8. Frequency response The frequency response of op-amp is used to investigate where the compensation capacitor Cc will cause magnitude of gain to begin to decrease and at frequencies below unity gain frequency. The second stage introduces primarily a capacitive load on the first stage due to the compensation capacitor
  9. Systematic Offset Voltage ' In the design of the two stage CMOS op-amp, it is possible that the design will have an inherent input- offset voltage. ' In order to ensure that no input-offset voltage is present, the derived necessary condition is (W/L)T (W/L)A (W/L)6 (W/L)S
  10. Feedback and Op-amp compensation Optimum compensation of op-amps is typically considered to be one of the most difficult parts of the op-amp design procedure. The compensation of op-amp includes stability of closed-loop configuration and good settling time characteristics.
  11. Continued.. The use of a Miller capacitance for compensation is called pole-splitting compensation because when Cc is increased, the dominant pole wpl moves towards lower frequency without affecting the second pole wp2 making the op-amp more stable. The lead compensation can be achieved using the value of Rc in the op-amp design which can be given as 1 1.2gml
  12. Making compensation independent of process and temperature The lead compensation can be made process and temperature insensitive by making Rcgm7 product constant i.e., (W/L)7 RcgmT (W/L)12

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