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LNA

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Published in: Networking
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Low Noise Amplifier Design

Najeemullah B / Hyderabad

8 years of teaching experience

Qualification: M.Tech (Moguls Institute of learning - 2007)

Teaches: Algebra, Computer Science, Mathematics, Physics, B.Tech Tuition, Electronics, M.Tech Tuition, Railways Exams, RRB, Sub-Inspector Exam, UGC Exams, Chemical, Electrical, Embedded Systems, Hardware Training, Informatica, MCA Subjects

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  1. DESIGN OF crvlos LNA By NAJEEMULLA BAIG
  2. Antenna BPF Front end Conventional GPS Receiver Mixer 2
  3. The block diagram of the dual conversion super-heterodyne architecture Antenna mixerl 3
  4. Architecture Selection ofLNA I.OAD I.OAD IOA.D Single Ended Architecture is selected as incoming signal from antenna is single-ended. (a) Single-Ended (b) Double-Ended LNA Schematic
  5. Single —Ended LNA with Current mirror voo ref ca VI 4 6uV •l .57.54GHZ C RI Ml •This circuit is basically a common source (CS) trans-conductance structure (Ml ) •Transistor M3,Rref and R2 essentially forms a current mirror with Ml . Voui •Current mirror circuit is is used to provide bias for Ml. •All the parameter values obtained based on NF optimization method. L3,Rl and are used to tune a particular frequency, here the frequency 1.5754GHz. •C2 blocks any DC coming from input. 5 •Increase in Livalue improves NF
  6. Inductive degeneration of source Small signal model of MOS in The input matching condition can be given as Inputämpedance S(Lg -k +
  7. Finding values of inductance, capacitances and widths of transistors Designing L2 using the real part matching condition: Rs=75Q, Unity gain frequency fT=25GHz, 211fT=gm/C Ls=L2, real part of input impedance (g /C )L m gs 2 , L2=O.5004nH Considering slightly higher value for 1-2 than calculated value, since the noise consequences of excessive inductance are much less serious than for insufficient inductance (H.Lee). Designing Ll using NF specification: < 2 (Bosco Leung) Solving yields 1 3 Let Ll -9.71667nH. 3 7
  8. Continue... Desiqninq C=C s and hence (W/L)l,using imaginary part matchinq condition: Using the matching condition /wcC With and using Ll values, Where fc=l .5754GHz operating frequency of LNA 1 = 847.77 fF 10.19413 We have that for a transistor operating in saturation region. Taking 1-1=0.18um minimum channel length allowed for this process and for this 0.18um process Cox=8.85 *10-3 F/um2. -15 847.77 x 10 x 169.49 = 798.269m , 2 cog 3 8
  9. Simulated Schematic of Single —Ended LNA with Current mirror q -9.71667nH, cg=912fF, 1-2=0.5004101-1, Cl =46.2fF, 4=10.213nH RI =4.6KQ, Rref=500Q, R=4.6KQ 9
  10. Continue... •Maximum finger width allowed by the tool is 100um so minimum of 8 fingers are required for W=798.269um, and M3=105um (a fraction of Ml ) with two Fingers gives NF=654mdB. •Where as Ml , M2 transistors with 15 fingers (each 53.2um) gives NF= 643mdB current through Ml =15mA. •We can reduce M3 width to 10.5um and Ml , M2 transistors with 8 finger but current through Ml is very high which is around 105mA, NF=583.55mdB. •Finally Ml , M2 transistors width 798.269um is divided into 15 fingers as optimum number of fingers which reduce gate resistance, as in low noise applications, the gate resistance must be one-fifth to one tenth of l/gm (RAZAVI). These reading are with respect to VDD=I .5V. 10
  11. Test-bench ofLNA consisting of both schematic and layout symbols •vdd
  12. Input-output waveforms v TCI 6 4 2 2 "VT(" / vout. 3.3004 3.3003 3.3002 3.3001 3.3 3.2999 3.2998 3.2997 3.2996 VT('I/vout L '"3 3.30015 3.3001 3.30005 3.3 3 .2ggg5 3.2ggg 3.29985 7.586ns 3.0 4.0 5.0 -2.13UV 7.0 8.0 10 time
  13. SNO 1 2 3 4 5 3.3 2.7 2.2 1.5 1.2 (mdB) 666.1 604.89 659.8 646.45 782.49 Gain (dB) 44.86 43.02 4426 45.06 42.74 (mdB) 542.09 580.31 632.52 618.23 745.06 Gain L (dB) 31 .96 31 7997 31 7821 32.184 30.992 These values met the required specification of 20 — 40 dB gain for LNA 13
  14. Noise ? / g " ? e " e " 0- 1 . 5 7 5 3 H z 5 64.79 rn d B 12 S 100 7 S. 0 ? ? S 0.0 2 S. 0 -2 S . 0 freq (Hz)
  15. LNA-with extra supply for biasing Ml ind l; *ill NNE nut. yout utl h Ihl 15
  16. With extra supply to bias Ml vgs=o.6V, NF=118mdB, Gain = 41.82 dB, at the frequency 1.574GHz. Here NF is decreased by a factor of 5.5 but extra power supply is required for V gs and gain has decreased 16
  17. Test-bench for LNA with external bias for Ml Tools Design Vändow Edit Add aleck Sheet. Options Migrate 'Odd abc 7ØØ>Øm vout PORT 2 vout ORTIZ
  18. NF Vs Frequency for LNA with out current mirror circuit 1,5754GHz 118rnd8 freq (Hz) 18
  19. During drawing of layout at each step it is better to check DRC because if total layout is drawn and then DRC is done finding errors is very difficult they will be in large number if not drawn properly. After layout is drawn extraction of Layout is done and extracted layout is compared with schematic using LVS tool for Parameters, W/L for transistors and values for linear elements and logical. 19
  20. Design of mixer considering IIP3 IIP3=5dBm, power-I Omw, VDD=3.3v, k'=170uA/V2 for 0.18um CMOS technology. Assuming that local oscillator is not switching finding (W/L) 1 (6.13) From above equation AIP3=0.563v and we have AIP3=4sqt (2/3) (Vgs-vt) (Vgs-vt) = 0.1 71464282 Using Ids equation at saturation and K' we can get W/L -1200.480192077 for L=O.18um W=216um. 20
  21. Mixerl by considering llP3 Tools Design Vändow Edit Add Check Sheet Options Migrate I .øsø•24K— neig netg2 net 11 I-COØ21e-ØB vdd! 6.gg432öinductar" vddl- -v2=aøørn :anøn undir gn VINS net 12 vdd ! an-ah *4ØØn ngers:l abc and netl 12 netlØ netlØ8 vbiøs fid! .gnd netg2 e r Shbtll vbias "inductor" 9 rod:2Øu net93 bios gn gerz 2 Here mixer 1 schematic is shown with W of Ml =216um and considering two fingers for Ml. Taking M2, M4, M5, M6 widths as minimum available and L=0u18um. Width of M3=1 Oum optimized for NF.
  22. VDD=3.3V S.NO 1 2 3 4 5 6 7 8 LO Voltage 0.7 0.8 0.9 1.0 1.1 1.2 1.5 2.0 (dB) 16.270 14.992 15.019 15.099 15.175 15.24 15.43 28.18 llP3(mdB ) 20.1628 19.6400 18.9593 18.17597 17.29795 16.311 12.3953 Gain (dB) 6.5190 6.1502 5.6301 6.02753 6.11590 5.8847 5.8740 6.2310 VDD=2.7V LO voltage =o.7V, gives NF=16.83dB, llP3=20.22557mdB and gain=5.5467dB. From this we can observe that as VDD decreases NF, IIP3 increase gain decrease, 22 power consumption also decrease.
  23. N/A

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