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ADC

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Published in: Networking
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Design of Analog to Digital Converter

Najeemullah B / Hyderabad

8 years of teaching experience

Qualification: M.Tech (Moguls Institute of learning - 2007)

Teaches: Algebra, Computer Science, Mathematics, Physics, B.Tech Tuition, Electronics, M.Tech Tuition, Railways Exams, RRB, Sub-Inspector Exam, UGC Exams, Chemical, Electrical, Embedded Systems, Hardware Training, Informatica, MCA Subjects

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  1. Importance of ADCs and Design
  2. Introduction & Importance of ADCs Analog-to-Digital Converters (ADCs) play an important role in ever-increasing Digital world. The advancements seen in Digital world continuously pose challenges to improve and develop new ADC architectures. High-end applications like Mobile systems, Image recognition, Digital receivers, Cellular base stations and Fast Ethernet require ADCs for processing natural signals in digital domain.
  3. Pipeline ADCs The Low Power and High resolution ADCs can be achieved by Pipelined architecture designed for high sampling rates. This Pipelined architecture offers Power and Speed advantages over Flash or Multistep approaches due to concurrent processing of the analog signal.
  4. General Block diagram of Pipeline ADC architecture Stage 1 Input X-Bit x-Sit Stage OAC x Sits resolved per st•ge Stage 2 Stage Stage Fig. Pipeline ADC architecture
  5. The pipelined architecture is known to be well suitable choice for achieving good dynamic performances and throughput as the underlying flash ADCs. The primary focus of this work is to investigate the various design techniques required to implement for Digital Video Broadcasting- pipeli n e ADCs Handheld(DVB-H) applications.
  6. PROBLEM CHARACTERIZATION Digital Video Broadcasting (DVB) is classified into 3 transmission specifications : DVB-S (S for satellite), DVB-C (C for cable) and DVB-T (terrestrial). DVB-H is an extension of DVB-T with advanced algorithms to facilitate signal reception at very high speeds, with less silicon implementation overhead and low power consumption.
  7. BLOCK DIAGRAM OF DVB-H RECEIVER SUBSYSTEM Antenna SAW Filter DVB-H Tuner 00 PLL 900 LNA ADC COFDM Demodulator ADC
  8. ' In DVB-H, the information is transmitted as IP datagrams at defined time-slots The signals used in DVB-H are COFDM modulated and can be used over 6, 7 and 8 MHz channel bandwidths The principal challenge in the design of DVB-H, DVB-T receiver subsystems is minimization of the power consumption of ADC
  9. Resolution Speed Power DNL INL SNDR System Level Specifications 10 bit 50 MS/s rnW 4 LSB < .5 LSB > 60 dB
  10. Pipeline ADC Architecture The proposed architecture is a 10-bit, 50 MS/s, 3-stage pipeline ADC designed in 0.18um CMOS process technology using Cadence tool. ' Each stage of the pipeline ADC consists of a Sample and hold, 4-bit Flash ADC, 4-bit DAC and an amplifier to provide the gain.
  11. Block Diagram of proposed Pipeline ADC Architecture bit •«ur.te ANALOG STAGE ADC LASH 16 4 bit attur•É 16 SUB ADC FLASH 4 bit DAC DAC Digital correction 10 bits
  12. Design Implementation The two major building blocks of this 3-stage pipeline ADC comparator(sub-ADC) and Operational Tran are conductance Amplifier(OTA). The sub-ADC is used to convert the incoming analog signal to low resolution digital signal. ' An amplifier is used to provide the gain required for subsequent stages of pipeline ADC.
  13. Comparator (sub-ADC) ' Comparator can be considered as a I-bit analog to digital converter and it is characterized based upon the low offset voltage, less power dissipation and low delay Pre-amplifier based comparator has less offset voltage and so it is mostly used for high resolution flash ADCs(n>3)
  14. Pre-amplifier based comparator There are t h stages in a based comparator: pre-amplification, decision circuit and output buffer. The decision circuit is heart of the comparator and can discriminate mV level signals whereas output buffer converts the decision circuit output into a logic signal.
  15. Circuit Diagram Preamp GND Ml.3 M14 Decision circuit Output buffer M15 M16 Vogt M18 Fig. Comparator circuit diagram
  16. Design Analysis t =2nsec; Vsph=Ov; q=O.1pf(assumption) vaH — VOL Iss/2 IDI = ID2 = Iss/2 = (V+ - V-) for ßB > ßA 13B 1 rss PA Here m2 where m = Kn(W/L) = Vin =
  17. Continued.. Here = (w/L)7 = (W/L)IO = (w/L)8 = (w/L)9 VOH — VOL AV = gm1/gm3 = gm2/gm4

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