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Mixer 2

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Published in: Networking
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Down Conversion Mixer from 577MHz to IF Frequency

Najeemullah B / Hyderabad

8 years of teaching experience

Qualification: M.Tech (Moguls Institute of learning - 2007)

Teaches: Algebra, Computer Science, Mathematics, Physics, B.Tech Tuition, Electronics, M.Tech Tuition, Railways Exams, RRB, Sub-Inspector Exam, UGC Exams, Chemical, Electrical, Embedded Systems, Hardware Training, Informatica, MCA Subjects

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  1. DESIGN OF CMOS MIXER2 By NAJEEMULLA BAIG
  2. Mixer2 Using this mixer the 577MHz frequency is down converted to 20MHz. The LO specifications are pulse width =897.666psec, pulse period =1.7953324nsec (557MHz) which is double of pulse width. In this mixer the tuned load (RLC) occupies large area when the layout is drawn.
  3. Schematic of mixer2 Is similar to mixerl the changes are W of Mitransistor is taken as 18mm with nine fingers each with 2mm.Because the normal calculation of Ml width using the method (considering IIP3) used for mixerl resulted into larger NF around 25dB and very good IIP3 around 27mdB, Even the NF improvement method used in LNA that is by adding gate inductor and source inductor also doesn't improved the NF, so to improve noise figure I have increased the width to 18mm.This is not larger when compared to inductor area which is used in this mixer2.
  4. For tuning 20MHz using RLC as load to the mixer2 Let inductor L=42.2898nH We have 1 211 Solving for C, gives 1 4112Lf 2 -1.49799nF. LC Since f = 20MHz 4
  5. Virtuoso@ Schematic Editing: nazeem_worklib mixer2experiment schematic Migrate Tools abc Design Vindow Edit Add Check Sheet Options '..ddl I Bø.G . *4.øøn natö .gnd net6Ø ngers= :EØån ØIIØ vbios 4..øem tØl.1Ø ngi-féö vdd net3 leø neu n 161 MN2 n et3i neteø nete 133 1 ne163 bias n fing
  6. Simulated Results for mixer2 'Following results shows that as VDD decreases noise figure degrades and gain decrease, but llP3 improves as VDD decreases. Power consumption also decreases with decrease in power supply VDD. 'In each table shown below we can observe that as LO voltage increases with respect to particular VDD, NF is improving and llP3 is degrading. This shows a trade-off between NF and llP3. Based upon requirement of noise figure, llP3 and power consumption one particular result can be selected. 'Some readings I am unable to simulate as the tool is having limitations with respect to the width of transistor and power supply. 6
  7. 1 2 3 4 5 VDD=3.3V LO voltage S .No 1.1 1.3 1.5 1.8 1.9 1.1 1.5 1.7 1.9 2.0 (dB) 6.61 5.77 5.65 5.60 5.58 VDD=2.7V LO S .No 1 2 3 4 5 6 2.0 voltage (dB) 6.9053 6.300 5.938 5.729 5.693 5.664 llP3( mdB) 18.8919 15.2722 12.46954 08.17687 04.83361 llP3( mdB) 19.0268 17.508 15.510 11 .028 8.7778 5.724 Continue... • Voltage Gain with respect to VDD=3.3V is -15.244dB. • For VDD=3.3, LO voltage =2.1, and WI=18mm tool is not supporting. Voltage Gain with respect to VDD=2.7V is -16.45dB 7
  8. VDD=2.2V LO S .No 1 2 3 4 5 6 7 1.1 1.2 1.3 1.8 1.9 2.0 2.1 voltage NF (dB) 7.0389 6.708 6.411 5.781 5.742 5.711 9.563 VDD=1.2V S .No 1 2 LO voltage (V) 1.1 1.2 NF (dB) 7.2415 6.9048 llP3( mdB) 19.119 18.424 17.637 11 .3864 9.2802 6.4305 2.208 llP3( mdB) 19.3072 18.6512 Continue... Voltage Gain with respect to VDD=2.2V is -17.45dB Voltage Gain with respect to VDD=1.2V is 8
  9. Here in table7.11 we can observe that noise figure is degraded for WI=9mm, when compared to w1=18mm. So, I used WI=18mm for my simulation results. 9

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