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Microprocessor & Micro Controller, RISC & CISC Processor

Home > PowerPoint Slides > Microprocessor & Micro Controller, RISC & CISC Processor
Published in: Computer Science | Electronics | Embedded Systems
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It is an important to all electronics, embeddede and computer science students. By this PPT they can learn about microprocessor and microcontroller.

Anuruddh S / Indore

10 years of teaching experience

Qualification: M.Tech (RGPV BHOPAL University - 2013)

Teaches: Advanced Excel, Basic Computer, Computer for official job, MS Office, School level computer, Hindi, IT & Computer Subjects, Computer Science, English, Mathematics, Physics, Science, Spoken English, Embedded Systems, Matlab, Robotics, Software Testing

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  1. Submitted by Mr. Anuruddh Sharma Asst.Professor (Department of Electronics and Communication Engineering) 2/3/2021 Anuruddh Sharma 1
  2. RISC-Based Architecture for Computer Hardware 2/3/2021 Anuruddh Sharma 2
  3. Contents Abstract Introduction Problem domain Solution Domain Instruction set Hardware domain Methodology Conclusion Application domain Future work References 2/3/2021 Anuruddh Sharma 3
  4. Abstract Computers are essential electronic devices for regular life. Their smartness comes as a direct result of the decisions and controls that microprocessor make. New applications and presence of FPGA or ease of ASIC leads computer engineers to use embedded systems to develop high performance technology that can achieve high speed processing, small size and low power consumption by the use of custom made microcontroller. Embedded systems are necessary to understand the basic operation of computer system, mainly control unit, memory unit and data unit. This work shows the design and functional implementation of a 16-bit RISC processor based on Harvard architecture. Which can be used as a soft core for FPGA embedded designs mainly for control and automation applications. 2/3/2021 Anuruddh Sharma 4
  5. Introduction The traditional approach to develop a digital system was to use a set of interconnected digital integrated circuits like counters, buffers, logic gates and memory. That task required lots of analysis, testing and the need to adapt the design to the hardware's inherent limitations (speed, response time, power consumption, etc.) which resulted in capped headroom for development. At present time, technological advance has brought new options like programmable logic as Complex Programmable Logic Devices(CPLD) or Field Programmable Gate Arrays (FPGA)with more sophisticated simulation and design verification environments which enable engineers to reach new levels of complexity and robustness, while greatly reducing the time between development and implementation. 2/3/2021 Anuruddh Sharma 5
  6. Components of a microprocessor/controller CPU: Central Processing Unit I/O: Input / Output Bus: Address bus & Data bus Memory: RAM & ROM Timer Interrupt Serial Port Parallel Port 2/3/2021 Anuruddh Sharma 6
  7. General-purpose microprocessor CPU for Computers. Commonly no RAM, ROM, I/O on CPU chip itself. Many chips on motherboard CPU General- Purpose Micro- processor Data Bus RAM ROM 1/0 Port Serial Timer COM Port 2/3/2021 Address Bus Anuruddh Sharma
  8. Microcontroller A single-chip computer On-chip RAM, ROM, 1/0 ports... Example : Motorola's 6811, Intel's 8051and PIC 16X CPU Port 2/3/2021 RAM ROM A single chip Serial Timer COM Port Microcontroller Anuruddh Sharma 8
  9. Comparison of Processors Processors are classified in three ways: Semiconductor technology (TTL, CMOS, ECL) Width of data format (4-bit,8-bit, 16-bit,32-bit, 64-bit) Instruction set (CISC, RISC) 2/3/2021 Anuruddh Sharma 9
  10. Types of Processor Architecture Von Neumann Architecture: Memory Data and instructions address bus CPU data bus [21 Single storage to hold both instructions and data. Both are stored in random access memory (RAM). 2/3/2021 Anuruddh Sharma
  11. Harvard architecture: Program Memory instructions PM address bus PM data bus DM address bus CPU DM data bus Data Memory data only a Separate storage for instruction and data. a Instructions can be stored in ROM while data memory requires read-write memory. 2/3/2021 Anuruddh Sharma
  12. Super Harvard Architecture: Program PMaddressbus Memory instructions PM data bus CPU Instruction Cache )Maddressbus DMdatabus Data Memory data only [21 a Same as Harvard but use additional memory called Cache memory. 2/3/2021 Anuruddh Sharma
  13. Problem Domain Few years back it was mandatory to use a microcontroller as it is to design a embedded system. Problem being the difficulty of designing a microcontroller and more over implementing it. NO FPGA were available and ASIC development was too costly and time consuming. 2/3/2021 Anuruddh Sharma 13
  14. Solution Domain Following options are available while developing a custom microcontroller I-RISC architecture or CISC Architecture 2-Schematics or HDL 3-Veri10g or VHDL 2/3/2021 Anuruddh Sharma
  15. Instruction Set @ The instructions needed were classified according to its purpose type in three groups: I-Operations (Arithmetic and Logical) 2- Program Control (Jumps) 3-Data Manipulation (Load and Storage) 2/3/2021 Anuruddh Sharma 15
  16. Continue... .. Syntax Micro- operation Mnemonic OR SHL SHR 2/3/2021 escription ddition Subtraction Immediate addition Immediate subtraction ogic AND ogic OR ogic NOT Shift register left Shift register right Immediate jump Jump to register D OR Rd Rd Rd Rd Rd d d Rd-Rs Rd-Rs Rd-k Rd-k SEIL Rd SHR Rd JNR Rd Anuruddh Sharma d NOT (Rd) (11+1) Rd(n), Rd(o) (n) Rd(n-l) Rd(7) C PC+k C Rd
  17. Fetch Continue Decode Insåucåon Reorder Buffer Execute Reüre [31 2/3/2021 Instructions Completed Insåuciion Buffer Anuruddh Sharma
  18. Continue Sts Sts 2/3/2021 01 01 Functional Flow Summary Anuruddh Sharma
  19. fick 8 Continue -rtck 9 instructon 1 IF 2/3/2021 Ir.structco 3 Ir.structm Insttuc•oon 7 Anuruddh Sharma [31 19
  20. Hardware Domain Program Memoryr instructions only 2/3/2021 PM address bus PM data bus CPU DM address bus DM data bus Anuruddh Sharma Data Mem01Y data only 20
  21. A. B. C. D. E. F. G. 2/3/2021 Program Counter (PC) ROM Program Memory Instruction Registers and Decoder General Purpose Registers (GPR) Arithmetic-Logic Unit (ALU) RAM Data Memory Control Unit Anuruddh Sharma Continue 21
  22. Methodology Entry Design Oos•gn i rnprernentatiort Xilinx Device Programming Annotation Design Verification Behavioral Simulation Simulation Static Timing Analysis Timing Sirnutation Verification FPGA Design Flow Overview After file synthesis with the Xilinx XST tool and the simulation analysis shown above, some numerical results were obtained These results reflect the hardware resources consumption and timing performance of the processor. 2/3/2021 Anuruddh Sharma 22
  23. Proposed design of processor Arithmetic and Logical Unit (ALU): Perform basic arithmetic and logic operations. Arithmetic operation are addition, subtraction, multiplication, addition with carry, subtraction with borrow etc. Logic operation are NOT, AND, OR, NAND, NOR, XOR, XNOR etc. 2/3/2021 Anuruddh Sharma 23
  24. Simulation Results clk rst start PLUM 0 ALU(I o instr(1 O} IR opcode(30 R2(1 a o z 2/3/2021 R TL schematic view of 16 bit processor Anuruddh Sharma 24
  25. 65472 Continue 65472 14336 1 6'hFFCü Now: 2000 ns CV[1 RÜ[1 5:Ü] R2[1 5:ü] R3[1 PC[1 5:ü] start 2/3/2021 Ons 1 4336 13311 1 6'h33FF 1 7'hZüüüü 163 14336 1 7'hZFFCü ADD Operation Anuruddh Sharma 1 6'hFFC.ü 1 7'hZFFCü 25
  26. ns 9 9 91 9 9 9 9 91 9 9 Now: 2000 n; RD[1 R2[1 5:0] PC[1 5:0] UI st UI start 1023 1 7h3.3FF 1 Continue 1 200 65412 ? ElhFFCD 65412 1 61h. 1 61h. 1 61h. 1 71h. 1 ? E'hFFCO filhO•? filhü•? filhD•? ElhDC 1 71hZDDDD 1 71hZFFCD 1 ? 420 1 71hZFFCO 1. filhD•? 171hZFFCD 2/3/2021 XOR operalion Anuruddh Sharma 26
  27. Conclusion a It gives a great margin for modification and improvement of a current design. The simplicity of the design —based on functional blocks its easy to understand how each part of a modern computer works, its relationships and to materialize theoretical concepts into functional devices. Obtained circuit can be used as a soft core perform this work one can observe the flexibility of the development platform, censor for FPGA designs that would like to add a Central Processing Unit (CPU) to handle peripherals or other devices. a The processor is based on the Harvard architecture, in which the size of the instructions is not related to the size of the data, and therefore it can be optimized in a way that any instruction occupies a single position of program memory, thus obtaining greater speed and a minor program length. Also, the access time to the instructions can be superposed with the one of the data, obtaining a greater speed in each operation. 2/3/2021 Anuruddh Sharma
  28. Application Domain The program used to evaluate the performance of the CPU must make use of all type of instructions to manipulate the stack, execute subroutines and access RAM. With a view to meet the requirements above, a program that calculates . 2/3/2021 Anuruddh Sharma 28
  29. Future Work In order to obtain a more sophisticated architecture we can add some advanced techniques like pipelining, interrupt handler and input/output controllers obtaining a competitive general purpose 16 bit RISC processor. 2/3/2021 Anuruddh Sharma 29
  30. Re erences [Il The 8051 Microcontroller and Embedded Systems,Muhammad Ali Mazidi. [21 Computer System architecture by M.Morris Mano. [31 Embedded System Design, Vahid/Givargis. [41 Advanced Microprocessor and peripheras by Ray Bhuchandi. [5] Antonio H. Zavala, Jorge Avante IR., Quetzalcoatl Duarte IR., J. David Valencia P. RISC-based Architecture for Computer Hardware Introduction, 20111EEE. [6] www.Xilinx.com/itp/xilinx10/isehelp/ise c_fpga_design flow overview.htm. [71 Verilog HDL:A guide to Digital design and synthesis ,by Samir Palnitkar. [81A verilog HDL Primer, J.Bhasker. [9]H. ElAarag, "A complete design of a RISC processor for pedagogical purposes,' Journal of Computing Sciences in Colleges, vol. 25, Issue 2, pp. 205-213, 2009. [10] M. Becvar, A. Pluhacek, J. Danecek, "DOI): a CPU core for teaching basics of computer architecture," Workshop on Computer architecture education, Article No. 4, 2003. 2/3/2021 Anuruddh Sharma 30
  31. List of Publications A 16-bit RISC processor for computer hardware introduction, IRACST - Engineering Science and Technology: An International Journal (ESTIJ), ISSN: 2250-3498,V01.2, No. 3, June 2012. A 8-bit RISC processor using Harvard Architecture, IJARCET International Journal of Advance Research in Computer Engineering & Technology (IJARCET), ISSN: 2278-1323, vol.l, No. 5, July2012. 2/3/2021 Anuruddh Sharma 31
  32. THANK YOU Anuruddh Sharma 2/3/2021 32

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