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delay flipflop which gives the same input as output with some delay

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D-FF Delay flip flop

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it is basically s r flipflop but their inputs are complemented.it isused as an delay element

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D FF ia also known as data delay FF.

in very simple words, output follows input with a propogation delay of unit 1.

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D-FF is a modified structure of RS-FF. Though all types of flipflops are used for storing data, D-FF send a 'data' from input to the output with delay. So it is used for data transmission in communication(i.e. shift registers)

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In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems

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The D flip-flop tracks the input, making transitions with match those of the input D. The D stands for "data"; this flip-flop stores the value that is on the data line. 

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It's a "data-delay" Flip Flop.

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The D stands for "data"; this flip-flop stores the value that is on the data line. It can be thought of as a basic memory cell. A D flip-flop can be made from a SR (set/reset) flip-flop by tying the set to the reset through an inverter. 

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D FLIP FLOP

The working of D flip flop is similar to the D latch except that the output of D Flip Flop takes the state of the D input at the moment of a positive edge at the clock pin (or negative edge if the clock input is active low) and delays it by one clock cycle. That's why, it is commonly known as a delay flip flop. The D FlipFlop can be interpreted as a delay line or zero order hold. The advantage of the D flip-flop over the D-type "transparent latch" is that the signal on the D input pin is captured the moment the flip-flop is clocked, and subsequent changes on the D input will be ignored until the next clock event.

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The D flip-flop is widely used. It is also known as a "data" or "delay" flip-flop.The D flip-flop tracks the input, making transitions with match those of the input D. The D stands for "data"; this flip-flop stores the value that is on the data line. It can be thought of as a basic memory cell..The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value becomes the output. At other times, the output Q does not change.

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The D flip-flop is a modification of the clocked SR flip-flop. The D input goes directly into the S input and the complement of the D input goes to the R input. The D input is sampled during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to the set state (unless it was already set). If it is 0, the flip-flop switches to the clear state.

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