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Low Power Design Methodologies

Published in: Physics
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Low Power Design Methodologies for Mobile Communication

Najeemullah B / Hyderabad

8 years of teaching experience

Qualification: M.Tech (Moguls Institute of learning - 2007)

Teaches: Algebra, Computer Science, Mathematics, Physics, B.Tech Tuition, Electronics, M.Tech Tuition, Railways Exams, RRB, Sub-Inspector Exam, UGC Exams, Chemical, Electrical, Embedded Systems, Hardware Training, Informatica, MCA Subjects

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  1. Low Power Design Methodologies for Mobile Communication
  2. INTRODUCTION The rapid development of multimedia applications and the Internet leads to the demand of mobility for these services. ' Key parameters for performance of a mobile terminal are — power consumption of the implementation. — long stand-by and talk times. This presentation discusses the problem of consumption in system on chip (SOC) design for applications and presents methodologies for optimized design. power mobile power
  3. ' Power consumption is a critical parameter in mobile battery-operated systems. ' parameters like operating and stand-by times have the main effect on the customer's choice in buying a mobile phone. ' size and weight of the device are determined by power consumption, as the battery of the handheld device mainly contributes to these criteria. ' Insufficient heat removal in narrow-spaced terminals, calls for optimizations concerning power consumption.
  4. TYPES OF POWER CONSUMPTION IN INTEGRATED CIRCUITS ' For power optimization of integrated circuits it is relevant to understand the causes of power consumption. diagram of the CMOS inverter example in VDD out n off n sat p sat poff cu VDD vss VDD-VT V,
  5. Without switching activity either the PMOS or the NMOS transistor is switched off. Sub- threshold leakage currents through the transistor channel and reverse saturation currents in the diffusion regions of PMOS and NMOS tranqiqtnrq hoth the qtntir, power consun avr stat DD (l)
  6. The static power consumption is temperature dependent and mainly given by transistor geometries W and L. ' Leakage power is the major concern for circuits in stand-by mode. Since the gate length of CMOS technologies decreases, this effect becomes more and more important due to the increasing channel leakage current when the transistors are switched off. ' For a short period of time, both NMOS and PMOS transistors are in saturation and simultaneously active. An instantaneous short-circuit current goes through the circuit, causing the short-circuit power consumption Pshort (VDD-2.Vth)3.r.a short 12 L
  7. This power is very small and can be neglected if the design is dimensioned and layouted properly. ' During dynamic operation charging effects of parasitic wiring and load caoacitors cause the dynamic ' Power consumption in digital circuits is usually dominated by this effect. Approaches for reducing the dynamic power consumption by scaling the contributing parameters will be described.
  8. Power Estimation on high abstraction levels ' Partitioning is already done on system simulation level, dividing the required functionality into hardware and software function blocks. ' In this design phase a straight-forward accurate and definite simulation of the power behaviour is hardly possible since the system level just describes the system functionality by a set of abstract mathematical equations. ' Exact power information can only be obtained for implementation related descriptions
  9. ' On system level two main approaches for power estimation are established. 1. 2. 3. 4. 5. Approach 1 One approach is resting upon the estimation of the number of operations algorithmic level and on complexity/transition activity on implementation level. The estimated capacitive load is added to a model library. The power contribution of each active circuit module in each clock cycle is added. Along with this, a model of component activity during the desired operations is required. This approach is based on the use of a software test bench as stimulus for the simulation.
  10. ' Approach 2 System Simulation Transmitter Chanrl Receiver FPGA Interface 1. 2. 3. Figure 2: Hardware/software co-simulation for power estimation Figure 2 shows that simulations take place in the usual system simulation environment which is the fast prototyping, Using Iow- power FPGA implementations. For power estimation a FPGA platform is added and a hardware/software co-simulation is applied. Measurement results are entered into macro models that are stored in a library. The absolute power values of FPGAIs and integrated circuits can not directly be compared since their power situation is different.
  11. Low-Power Design Concepts Wrong decisions on system and algorithmic level, e.g. about partitioning or power management, can not be corrected on lower levels. ' parallelism or pipelining, redundancy, RTL clock gating and energy-optimized coding style (e.g. the use of 'if' instead of 'case') lowers power consumption up to a certain degree. The power saving capabilities in digital logic level are bound to the availability of optimized standard cells.
  12. Concepts on higher abstraction levels ' In telecommunication applications flexibility is an issue, as it enables multi-functional and multi-standard operations, and adaption to environmental conditions ' General processors like ARM are flexible in a highest grade but not efficient concerning chip area and power consumption, providing not more than a few MIPS/mW. ' Power efficiency and area requirements can be improved by using alternative architectures like softwa re programmable hardware DSP or reconfigurable processors, but on cost of flexibility.
  13. ' An effective method of power optimization on medium abstraction levels is the reduction of switching activity. — The insertion of different clock domains, known as clock rating, allows reduction of the switching activity mainly in data oriented paths. — Disabling whole clock domains using the clock gating technique is most efficient in control orientated paths. Gray coding reduces both the average number of logic transitions per clock and the overall number of transitions for a cycle
  14. Concepts on implementation level The most effective way to reduce dynamic power consumption on implementation level is scaling of the supply voltage due to the quadratic dependence. ' Limiting parameter is the propagation delay that ir fi rst-or 2 "01tages. A (4) vth)2
  15. This equation is illustrated in Figure 3 for a typical deep- submicron CMOS technology. 50 40 30 20 10 05 Figure 3: Dependence of propagation delay on the supply voltage ' It can be seen tnat tne propagation delay increases drastically as the supply voltage approaches the threshold voltage
  16. ' Any voltage reduction must be balanced against performance reduction which leads to methodologies like architecture driven voltage scaling. ' To obtain an energy-optimized solution a variety of supply voltages is required for different function blocks of an on-chip system. ' In practice this is hard to handle if the number of different supply voltages is high. ' Another issue is parameter variation in CMOS to overcome these problems processes, introduces a local supply voltage regulation.
  17. The block diagram in Figure 4 shows a PLL-like control loop containing a DC/DC converter for local supply voltage generation. speed requirement Controler DCDC Circuit Test Circuit Figure 4. Performance-driven voltage scaling
  18. ' A reduction of the operating frequency increases the propagation delay and doesn't reduce the total power consumption for a given performance Frequency reduction can be useful for nontime- critical algorithms due to the reduction of the peak current. The lower battery discharge current has a direct impact which leads to higher charge availability.