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Low Power Layout Methodology

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Published in: Physics
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CMOS Low Power Layout Design

Najeemullah B / Hyderabad

8 years of teaching experience

Qualification: M.Tech (Moguls Institute of learning - 2007)

Teaches: Algebra, Computer Science, Mathematics, Physics, B.Tech Tuition, Electronics, M.Tech Tuition, Railways Exams, RRB, Sub-Inspector Exam, UGC Exams, Chemical, Electrical, Embedded Systems, Hardware Training, Informatica, MCA Subjects

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  1. Low Power Layout Methodology power optimizations on layout level is the minimization of device parasitics which determine the static and dynamic MOS transistor behaviour which influence the power consumption. Minimization in that case means area reduction of the parasitic device and its related device area. This can be obtained by techniques like merging and sharing of MOS diffusion area and wells.
  2. Low Power Layout Methodology The use of dedicated MOS transistor geometries like closed, iii. waffle, finger or hexagon arrangements reduces parasitic drain-bulk and stray capacitances. Further improvement is obtained by the use of transistor folding techniques that decrease wire capacitances and resistances. For utilization of these optimizations in a digital design they have to be applied to standard cell libraries.
  3. Low Power Layout Methodology All these effects are related to the primitive device level it is worth to optimize them in a bottom-up design. power and noise optimization at cell level power optimization at sub-cell level power optimization at prillliti\.æ device level power optimized P&R strategy low noise techmques stick diagam optimized abutment of primitive devices reduction of device and wire parasitics shaping, folding and mergng techniques bottom-up design methodology Figure 7: Low power layout methodology
  4. The optimized primitive devices are composed in the symbolic sub-cell level and finished on the physical cell level. Stick diagrams with emphasis on keeping the dynamic signal wires short are drawn. Clock wires have to be shaped for minimum wire length and capacitance. using metal wires for intrinsic routing leads to an area capacitance reduction of factor 3 compared to poly wires.
  5. A drawback of the layout techniques is the lack of support by standard design environments. Special geometries, e.g. closed gates, lead to an insufficient support by standard models like bsim3v3. Energy reduction by lowering supply voltages can also be introduced to the digital top level layout. This assumes the availability of standard cell libraries that are characterized for the corresponding supply voltages.
  6. Different examples for a dual voltage P&R concept are illustrated in Figure 8. Here, 'H' and 'L' mark the two supply voltages. single-voltage approach in Figure 8a. i. a) single voltage approach +1 b) one horizontal power track c) two horizontal power tracks Figure 8: Place and route concepts
  7. ii. iii. one horizontal power track in each standard cell row, divided by power-stop cells between the different supply regions in figure 8b. Figure 8c deals with two horizontal power tracks in standard cells that provide dual-supply connections. The price for the dual-voltage layout is a slightly larger area due to the power-stop cells and additional vertical power rails.
  8. Conclusions Variety of approaches for reduction of power consumption have been discussed with focus on CMOS digital integrated circuits. Optimizations on algorithmic and architectural levels of a design may have a major impact on power. Methodologies like clock gating or coding are useful to further decrease power consumption. Main parameters for power reduction on circuit level are the switching activity and the supply or signal voltage. Supply voltage partitioning is supported by the presented performance driven voltage scaling concept.

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