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8255-PPI

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Published in: Electronics
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It is PPT about the Programmable Peripheral Interface designed for interfacing I/O device to Microprocessor

Sasikar A / Chennai

10 years of teaching experience

Qualification: M.E-Applied Electronics

Teaches: Computer, Electrical, Electronics, Mathematics

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  1. UNIT - IV PERIPHERAL INTERFACING Study of Architecture and programming (interfacing with 8085) of ICs: (1) 8255 - PPI (2) 8259 - PIC (3) 8251 - USART (4) 8279 - Key board Display controller (5) 8253 - Timer/ Counter and (6) A/D and D/A converter
  2. Need for an Interfacing reading data from an external device writing data into another external device
  3. -The task of connecting an 10 device to a computer system is greatly achieved by the use of Standard IC's known as 10 interface circuits, 10 Module, 10 System, Peripheral interface adapters, and the like. -Allows 10 devices of widely different characteristics to be connected to a standard system bus with a minimum of special-purpose hardware or software. - programmable. - intended to act as serial (slow devices) or parallel ports (multi-bit, bidirectional data path — high speed).
  4. 8255 Programmable Peripheral Interface (PPI) Intel Resigned for interfacing 10 devices with Intel 8085 & other small PPS. 40 pin package. 8 pins connect the 8255 to an 8 bit bidirectional CPU data bus. 24 pins are attached to several 10 devices and are programmable in that the functions they perform are determined by a control word issued by a CPU instruction and stored internally in the 8255. CW can specify a variety of operating modes. (Sync or Async).
  5. 8255 Programmable Peripheral Interface Circuit Data bus Address lines READ WRITE cs 8255 Data buffer 4 Read/write Control Logic Control Register CR
  6. Description 24 pins on the I/O side of the 8255 are divided into 8-bit groups designated A,B and C, each of which can act as an independent 10 port. Port C can be further divided into two 4-bit groups CA and CB and used as status or handshaking lines in conjunction with A and B ports. Two address lines Ao & Al select one of the three ports A, B and C for use in an 10 operation. (three addresses). The fourth address is used in conjunction with an output instruction of the form OUT CW to store an 8- bit user-specified CW in 8255.
  7. popops Iou s! SSZ8 b10d uoyoops b10d so 'ON'S
  8. Group B Port C (Lower -Y PC3-PC0) 1= Input ; 0= Output Port B 1= Input ; 0= Output Mode Selection Mode O ; Mode 1 o 1 BSR Mode 1/0 Mode Control Word Group A Port C (Upper > PCTPC4) Input ; 0= Output Port A 1= Input ; 0= Output Mode Selection Mode O ; Mode 1 Mode 2
  9. Continued Functions of CW: 1) It specifies whether A, B and C ports are to act as input, as output or, in the case of A and B only, as bidirectional 10 ports. 2) It programs certain C lines to generate handshaking and interrupt signals automatically in response to actions by an 10 device.
  10. Modes of Operation 1/0 Mode Mode O-Simp1e 10 Mode Mode 1- Handshake Mode Mode 2- Bi-directional Mode >Bit Set/Reset Mode
  11. To communicate with peripherals through 8255, three steps are necessary 1) Determine the addresses of the ports A, B and C and of the control register according to the chip select logic and address lines Al and Ao. 2) Write a control word in the control register. 3) Write I/O instructions to communicate peripherals through ports A, B and C. with
  12. Mode - O : Simple 1/0 Mode ' Ports A and B are used as two simple 8-bit I/O ports and Port C as two 4-bit ports. ' Each port can be programmed to function as simply an input port (or) an output port ' The input/output features in Mode -0 are as follows, 1) Outputs are latched. 2) Inputs are not latched. 3) Ports do not have handshake or interrupt capability.
  13. Mode - 1 : Handshake Mode Port A (or) Port B can be set for input (or) output operation. The bits from port C are used as control signals (used for handshaking). The features are, (1) Two ports (A and B) function as 8-bit I/O ports. (configured either as input or output ports) (2) Each port uses three lines from port C as handshake signals and the remaining signals can be used for simple I/O functions. (3) Input and Output data are latched. (4) Interrupt logic is supported.
  14. Input Control Signals Mode-I v/ STBbar(Strobe)- generated by a peripheral device to indicate that it has transmitted a byte of data. v/ IBF (Input Buffer Full)- is an acknowledgement by the 8255 to indicate that the input latch has received the data byte. v/ INTR- used to interrupt the CPU when an input device is requesting service. v/ INTE (Interrupt Enable)- internal flip flop used to enable (or) disable the generation of the INTR signal.
  15. Output Control Signals , Mode-I VOBFbar (Output Buffer Full)- is an O/P signal that goes low when the MPU writes data into the output latch. v/ ACKbar — input signal from a device that must output a low when the device receives the data from 8255 ports. v/ INTR INTE (Interrupt Enable)
  16. Mode - 2 Bi-directional Mode Port A is used as a bi-directional port with simultaneous input and output capability. Port C are used for handshake. (Handshaking signals are used to transfer data between devices whose data transfer speeds are not same.
  17. Not used, generally set=0 BSR Mode Bit Set/Reset Mode makes use of only port C. any bit of this port can be set (or) reset. Control word format in BSR Mode DI 000 = Bit O 001 = Bit 1 010 = Bit 2 011 = Bit 3 100 = Bit 4 101 = Bit 5 110 = Bit 6 111 = Bit 7 Bit Select s/R Set=l Reset=0
  18. Write initialization instructions for the 8255A to set up (i) Port A as I/P port in mode 0. (ii) Port B as O/P port in mode 1. (iii) Port C upper as an O/P in mode 0. Assume address of control word register as 83H. Determination of Control Word 95H MVI A, #94H or OUT 83H MVI A, #95H OUT 83H
  19. Thank Q

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