Operating System

Published in: Oracle Certification

108 Views

Basic Knowledge about Operating System and Types of Operating Sysytems

Kartheek G / Vijayawada

10 years of teaching experience

Qualification: M.Tech in Computer Science & Engineering

Teaches: Advanced Excel, Basic Computer, Computer for official job, MS Office, School Level Computer, Computer, IT, C / C++, Java And J2EE, Artificial Intelligence, Hardware Training, UGC Net, Blog Programming

Contact this Tutor

Computer Organisation The Von Neumann model uses a series Of registers. (a) Explain what is meant by the term register. (b) (i) Explain the purpose Of the Memory Data Register (MDR). (ii) Name two registers, Other than the MDR, that are used in the fetch-execute cycle. Register I Register 2 aln a multiprogramming ming environment, the concept Of a process has been found to be very useful in controlling the execution of programs. Explai n t he concept Of a process. iiln one model for the execution Of a program, there are five defined process states. Identify three of them and explain the meaning Of each. bThe transition of processes between states is controlled by a scheduler. Identify t wo scheduling algorithms and for each classify its type. iiA scheduling algorithm might be chosen to use prioritisatio n. Identify two criteria that could be used to assign a priority to a process. 2 a Three memory management techniques are partition ing, scheduling and paging. Give definitions Of them. iildentify two ways in which they might be combin ed. bSome systems use virtual memory. Identify which Of the techniques in part (a) is used to create virtua I memory. Explain three differences between the memory address register and the memory data register. d 2 Thesystembus comprises three individual buses the data bus, the address bus and the control bus. a FDr bus give e brief explanation Of its use. b Each bus has a defined bus width. j State what determines the width 0t a bus. ii Explain which bus will have the least wiCttL iii Explain the effectofchangingthe address bus from a 32-bit bus to 264-bit bus. 3 Thefetch stage of the fetch-decode-execute cyde can be represented bythe following statements using register transfer notatiorr [YCI b pc IPO + 1; (IMAR]] CIR Explain the meaning Of each statement The explanation must include definitions of the following items: MAR, pc, [l MOR, CIR. Explain the use of theaddress bus and the Cata bus for t'.vC Of the statements.
6 Parity bits can he used to verity data. (a) Tha following binary number is transmitted using even parity. Add the missing parity bit. Parity bit (b) In the following parity block, the first cnlumn contains tha parity bits, and tha last row contains tha parity byte A devica transmts the data using even parity (i) Cicla the error in the data transmitted Parity Data Parity byte 1 1 1 1 1 o o 1 (ii) Explain how you identified the error. 20.04 Virtual machine Although virtu al memory could be used I n a system running a virtual machine, the two are completely different concepts that must not be confused Also note that the Java virtua machine discussed in Chapter 7 (Section 7.05) is based on a different underlying concept. The princ' ple of virtual machi ne is that a process interacts directly with a software interface provided by the operating system. The kernel of the operating system handles all of the interactions with the actual hardware of the host system. The software interface provided for the virtual machine providesan exact copy of the hardware. The logical structure is shown in Figure 20.05. Application programs for virtual OS kernel Wlrtua I machine VMI Application programs for virtual machine VM7 OS kernel for VM2 Virtual machine VM2 •virtual-machine implementation software Hardware Figure 20.06 Logical structure tora virtual machine implementation
6.04 Assembly language instructions 1 Three in structionsfo r a processor with an accumulator as the single general purpose register are: LDD <address>for di rect addressing LDI <address>for indirect addressing LDX <address>for indexed addressing Instruction opcode LDM LDR LDD LDI STO Instruction operand caddres caddress> caddress> caddress> Explanation Immediate addressing IDading n to ACC Immediate addressing loading n to IX Direct addressing, loading to ACC Indirect address ng, loading to ACC Indexed addressing, loading to ACC Storing the contents of ACC In the diagrams below, the instruction operands. the registercontent, memory addresses and the memory contents are 211 shoven as denary values. a Consider the instruction LDL Ora'" arrows on a copy of the diagram below to explain execution of theinstruction. address Accumulator 104 Index register Memory content 114 Show the contents of the accumulator as a denary value after execution of the instruction.
Consider the instruction 107. i Draw arrows on a copy of the diagram telowto explain execution of the Instruction. Accumulator Index register Memory address 101 105 107 Memory Content 114 108 103 104 102 ii the contents oflhe accumulator as a denary value after execution of the instruction i Draw arrows on a copy Of the diagram below to explain the execution of the I nstruction 103. Accumulator Index register Memory address 103 104 105 105 Memory 114 112 110 106 104 102 ii Show the contents of the accumulator as a denary value after the execution. 2 Every machinecode hstfuction equivalent in assembly language. An assembly program will contain a;Tmbty language instructions. An assembly la program also contains components not directly transformed i MO machine code instructions when the program is assembled. b Name three types Of component Of a n assembly language program that are not intended to be directly transformed into machine code by the assemblet For one component, state its purpose. Trace the followingassembly language program using a copy of the tracetable prcvided. Nate that the LDI instruction uses indirect addressing. Assembly language program Memory address Memory content 105 108 201 Accumulator LDI 203 204 STO 201 INC STO STO 204 201 Acc ACC 201 Memory addresses 0 5
Classless inter-domain routing (CIDR) The first approach developed for improving the addressing scheme is called 'classless inter- domain routing' (CDR). This retains the conceptoF a netlD and a hostlO but removes the rigid structure and allows the split between the netlC and the hostlD to be varied tosuit individual need. The simple method used to achieve this is to add an 8-blt suffix to the address that specifies the number of bits for the netlJ_ If, fcr instance, we define the suffix as 21, that moans that 21 bitsare used for the netlD and there are 11 bits remaining (OF a 32•bit address) to specify hostlüs allowing?i, I.e. 2048, hosts. One example of an P address using this scheme is shown in Figure 2.06, The 21 bits representing the netlD have been highlighted. The remaining 11 bits represent the hostlD which would therefore have the binary value 11000001110. Binary code: netlD Dotted decimal notation: 195 12.6.14/21 Figure 206 CDR IPv4address suffix It should be acted that with this scheme there is no longer any need to use the most significant bit orbits to define the class. However, it does already existing Class A, B or C addresses to be used with suffixes 8, 16 or 24. respectively, TASK 2.02 an n;ample Of tha binary GOGG fer a Cla;s C aedratG in CIOP,fQrm7i. correspondingdotted decimal representation.
Can you tind out whether the processors in any systemsyou are using are described as RISC One of the major driving forces for creatng RISC processors was the opportunity they would prcvid2 for efficient pipelining. apelining is a form cf parallelism appliedspecifically to instruction execution. Other forms of parallelism are dscussed in Section 13.03. Pipeüning: instruction-level parallelism Tho underlyi ng principle ofpipelining i; that the fetch—decode-execute cycle described in Chapter 5 (Section 5.04) can be separated into a number of stages. One possibility is a five-stage model consistinE of: instruction fetch (IF) • instruction decode (ID) operand fetch (OF) Instruction execute (E) result Mitc back (WB). Figure shovvs howpiV*lininE would workwith this five stäee breakdown of instruction handlinz. For pipelinine to be implemented. the ccnstruction of the prccessor must have five independent units. with each handling one of the f ve Identified. This explains the need for a RISC processor lc have many register sets; each processor unit must have access to its own setof registers. Figure 19.01 uses the representation 1.1, 1.2 ard so on to define the instru:licn and the staze of the instruction. Initiallv onlv the first stape DI CISC / RISC Clock cycles 12 1.4 2.4 6 7 Figure 19.01 Pipelining for five-stage instruction handling
2 The tollowng table Shows assembly language instructions tor a processor one general purpose register, the Accumulator (ACC) and an Index Register OX). Instruction Op code LDD S 10 DEC < address> (addre < address> Direct addressing. Load the contents ot the location at the given address to ACC. Indexed addressing. Form the address from eackftess> + the contents Of the Index Register. Copy the contents of this calculated address to ACC. Immediate addressing. Load the number n to IX_ Store contents Of ACC at the given address. Add the contents Of the given address to ACC. Add 1 to the contents Of the register (ACC or 1K). Subtract from the contents Of the register (ACC or IX). Compare contents 0t ACC with contents Of address>. Following compare instruction, jump to it the compare was True. Following cornpare tvstruction, iurnp to if the compare Was False. Jump to the given address. Output to the screen the character whose ASCII value is stored in ACC. Return control to the operating system. (a) State what is meant by relative ad«ressing and indexed addressing. Relative addressing _ (b) The current contents of a general purpose register (X) are: (ivy x The contents of X represent an unsigned binary integel. Convert the value in X into denary. The contents ot X represent an unsigned binary integel_ Convert the value in X into hexadecimal. The contents ot X represent a two's complement binary integer. Convert the value in X into denary. Show the result on the general purpose register (X) after the following instruction is run INC X
Ill Ill | ?
5.01 The Von Neumann model of a computer system The simplest form of whet might be described as a computer system model or computer system architecture is usually attributed to John von Neurnann. Thisrecognises the factthdl he was the first to describe the basic principles in a publication. The model has the following bzsic features There is a processor, a central processing unit. The processor has direct access to a memory. The [lierr,ocy contains •stored program' Ivvhich can be replaced by another atary time) and thedata required bythe program. The stored program consists of individual instructions. The processor ekecutes instructions sequentially.
5.02 Central processing unit (CPU) architecture are complex; some ofthe complexitics will be discussed in Chepter [Sections lg.02 and IE.03). In this chapter the locus ison the fundaments's of the opprätion 01 an up tc&tc version of simple von Neumann computer system. Figure S,OL gives simplified schana:ir_ diagram Uf a processor that could be part of this simple system The dotted outline shows the boundary ofthe processor. The logical some of the ptocesscl is indete'. The arrows shaw passible directions of Faw Of dfita the following disn:ssion Will show. the data for some ofthe arrow an address an instruction. in general. data might be an instruction, an address tr value. Components of the CPU [he mcjor components of the CPU are the and logic unit (01 Arithmetic Logic unit) and the controi unit. As its Control Address control unit Arith Logic nit Other resisters implies, the resconsiblefor any arithmetic Figure 5.01 A schematic diagram cf the architecture of a simple CPI—I or logic pro:essing Lh3t might needed when a grogram is running The functitns afthe control unit are more di%ersc. One aspect contralling the flow of data throe.'ghout the processor and, indeed, throughout the compuler system At-other Sensurins that prosrarn
5.04 The fetch—execute cycle The name for this is the fetch, decode and execute cycle. This is illustrated by the flowchart in Figure 5.03. START Any instructions NO to execute? Fetch n control to interrupt*' andiing program instruction Any inter upts YES to be procesæd? Figure 5.03 Flowchart for the letch, decode and execute 5.03 The system bus A bus is a parallel :ransmission com;onentwith each separate wire carryinæ a 5inele bit. [t is impcrtant describe a bus as g hus does not Hold data. instead it tsa mechanism far data to be transferred trom one system component another. In the simple computer system described in fris chapter will be a system bus ihatramprises three distinct com;onents:the address bus. the data bus ane the contra' The diagram ot the CPU W', Figure shows the logical connection between each bus and a CPU ccrnponent. The address bus is connected to the MAR; data bus to the MOR; and the control bus to the control unit. The system bus allous data flCA'.' between the CPL', the memory, and input or output (I/O) devas as shown in the schern.atic diagram in F gure 5.02. The address bus CPU Memory Contra I bus Ad dress bus Data b LIS and Output Figure 502 A schematic diagram of the system bus The sale function Of the address bus i5to carry an This address is loaded on to the bus from the VAR as by the Cc•nuroL unit. The addrcss specifies a location tn memory which is due to receive data w from which data is to be read The address bus isa •one-wav street•_ It can only used to *2nd an addressto memory controller. It cannot be used to carry an address born the rnermory controller back ta the CPL]
20.04 Virtual machine Although virtual memory could be used in a System running virtual machine. the two are Completely different concepts that must rot he confused, note that the Java virtual machine discussed in Chapter 7 {Section 7,0S) based on a different underlying concept. The principle ot a virtual machine is that a process interacts directly with a software interface provided b/ the operating system. The kernei of the operariagsystem handles sil of the interactions with the actual hareware the host system. The software knterface provided for the virtual machine provides an exact copy of the hardyvare. The logical Structure is shown in Figure 20.06. Application programs for virtual machine VMI OS for vtn Virtual machine VMI Application progra ms for virtual machine VM2 OS kernel for VM2 Virtual machine VM2 Virtual-machine implernentation software Figure 20.06 Logical structure for a virtual machine implementation

We use cookies

Choose Country Code

Direction

Ask a Question

Report a Profile Issue

Operating System

Kartheek G / Vijayawada

Need a Tutor or Coaching Class?

Upload Study Notes