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Notes On Combinational Circuits

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Published in: Electronics
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Combinational circuits

Bikash B / Bhubaneswar

7 years of teaching experience

Qualification: M.Tech

Teaches: Mathematics, Physics, B.Tech Tuition, Electronics, Study in Australia, Embedded Systems

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  1. Combinational Circuits Mr. Bikash Kumar Behera
  2. Combinational Logic ' Logic circuits for digital systems may be combinational or sequential. ' A combinational circuit consists of input variables, logic gates, and output variables. ' The outputs are functions of inputs. n inputs Combinational m outputs circuit Fig. 4-1 Block Diagram of Combinational Circuit
  3. Design Procedure 1. 2. 3. 4. From the pspecifications of the circuit determine the required number of inputs and outputs and assign a symbol to each. Derive the truth table that defines the required relationship between inputs and outputs. Obtain the simplified Boolean functions for each output as a function of thee input variables. Draw the logic diagram.
  4. Half Adder A combinational circuit that performs the addition of two bits is called a half adder. The truth table for the half adder is listed below: Table 4-3 Half Adder S = x'y + xy' C = xy
  5. Half Adder —xyl + x'y C = xy Fig. 4-5 xoy Implementation of Half-Adder
  6. Full-Adder ' One that performs the addition of three bits(two significant bits and a previous carry) is a full adder. Table 4-4 Full Adder
  7. Full x 01 11 10 01 11 10 1 x S — x' y' z + x'yz'+ xy'z' + xyz 1 S xy + xz + yz xy + xy'z + x'yz Fig. 4-6 Maps for Full Adder
  8. Full Adder x z Fig. 4-8 Implementation of Full Adder with Two Half Adders and an OR Gate
  9. Half Subtractor ' Half Subtractor is a combinational logic circuit. ' It is used for the purpose of subtracting two single bit numbers. ' It contains 2 inputs and 2 outputs (difference and borrow). x 1 1 1 1 Difference (D) 1 1 Borrow(B) 1
  10. Half Subtractor
  11. Full Subtractor ' Full Subtractor is a combinational logic circuit. ' Thus, full subtractor has the ability to perform the subtraction of three bits. ' Full subtractor contains 3 inputs and 2 outputs (Difference and Borrow)
  12. Full Subtractor Difference(D) Borrow(B)
  13. Subtvactov
  14. Full Subtractor Borrow = X'Y+ (X Y)' Z
  15. Binary adder ' This is also called Ripple Carry Adder ,because of the construction with full adders are connected in cascade. cm co so Fig. 4-9 4-BitAdder
  16. Carry Propagation ' The signal from Ci to the output carry Ci+l, propagates through an AND and OR gates, so, for an n-bit RCA, there are 2n gate levels for the carry to propagate from input to output. ' Because the propagation delay will affect the output signals on different time, so the signals are given enough time to get the precise and stable outputs.
  17. Carry look-ahead Adder fig. 4-10 Full Adder with P and G Shown
  18. Carry look-ahead Adder q = AiBi Carry Propagating term Carry Generating term Output sum and carry Ci+l = Gi + PiCi q : carry generate Pi : carry propagate Co = input carry Cl = Go + poco C2 = Gl + PIC 1 = Gl + PIG o + C3 = G 2 + P2C2 = G 2 + P2G1 + p2p1Go + p p pc 2100 C3 does not have to wait for C2 and Cl to propagate.
  19. 4-bit adder with carry lookahead Carry Look ahead generaLcm- Fig. 4-12 4-Bit Adder with Carry Lookahcad
  20. Binary Subtractor Full Adder co Full Adder Full Adder Full Adder
  21. Binary Adder/Subtractor Fig. 4-13 4-Bit Adder Subtractor M = I—>subtractor and M co = O...>adder
  22. Decoder ' Decoder is a combinational circuit that has 'N' input lines and maximum of (2)N unique output lines. inputs Decoder 2 Outputs ' The name "Decoder" means to translate or decode coded information from one format into another, so a digital decoder transforms a set of digital input signals into an equivalent decimal code at its output.
  23. Decoder ' Active High Decoder - The output line that is active will be High(l) and rest all the outputs will be low(O). ' Active Low Decoder - The output line that is active will be High(O) and rest all the outputs will be low(l)
  24. 2:4 active high Decoder - ml -1110 - 1112-1110 - 1113-1110 D D D , 10) , 10) , 10) 2 (11,10)
  25. 2:4 active high Decoder
  26. 2:4 active Iow Decoder (11,10) - - 1110 - ml -1110 D ,10) , 10) 1113-1110
  27. 2:4 active low Decoder
  28. 3: 8 line Decoder
  29. ?????? = 0111 ?? = ?????? = ?? ?? ???? = ?????? = ?? ?? ???!?
  30. Block diagram of 3:8 active high decoder Decoder
  31. 7-segment Display b pattern ?ooco
  32. BCD to 7 —Segrnent Decoder Inmjt Signd a b c D BCD to 7eSegnent Decoder 7•Scynont Outputs
  33. Truth Table BCD to 7-segment Decoder Decimal Input lines Display Output lines Digit pattern ABC D a l) c c*efg 00101 1001 101 10 01 10000
  34. BCD to 7 -segment Decoder + 13,14, 15) + 13,14, 15) + 13, 14,15) + 13,14, 15)
  35. BCD to 7 —Segrnent Decoder CD CD OO 01 11 10 01 11 10 albaa a-Å+C+BD+Éj CD 01 11 10 c=B+C+D
  36. BCD to 7 -segrnent Decoder 01 11 10 oo o 1 x 1 01 o 1 x 1 11 1 O x x 10 1 1 x x g=BC+CÔ+BC +BC+A a A + C + BD + C + CD e—Bb+CD f-A+CD+BC+BD
  37. BCD to 7-segment Decoder ? 011 ? ? 0- ? ? ? ? ? ? 9 B ? C D
  38. Encoder encoder is the inverse operation of a decoder. ' It Converts Decimal to Binary. 2 input Lines ENCODER N output lines ' At any instant of time only input line should be active.
  39. 4:2 Encoder Encoder
  40. 4:2 Encoder
  41. Ambiguities in Encoder 1. 2. The output with all o's is generated when all the inputs are O and the output is the same as when Do is equal to 1. If two inputs are active simultaneously, the output produces an undefined combination.
  42. Priority Encoder ' Ambiguities present in the encoder can be overcome in Priority encoder. 1. 2. First ambiguity can be overcome by assigning an extra bit in output V(validity bit) which will be "1" if atleast one input is High else O. i.e valid inputs; V=l—>valid inputs. Second ambiguity can be overcome by assigning an input priority to the input lines to ensure that only one input is encoded.
  43. 4:2 Priority Encoder having priority inputs: D3 DI DO outputs: Bl, BO, V BI(MSB) Inputs Outputs
  44. 4:2 Priority Encoder having priority 'Fig. 4-23 4-lnput Priority Encoder
  45. ' Multiplexer is a combinational circuit that has maximum of (2)ndata inputs, 'n' selection lines and single output line. ' One of these data inputs will be connected to the output based on the values of selection lines. ' Since there are 'n' selection lines, there will be 2n possible combinations of zeros and ones. ' So, each combination will select only one data input.
  46. 2 x 1 Multiplexer Function Table Truth Table
  47. MUltiplexer F so SIS 013 Function Table s I s012+SlS011 +

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