Course Details

VHDL Learning Programme is comprised of the following:

The "Shape" of VHDL

Demo: Multiplexer

Lab 1: Using the Tools

Documentation in VHDL

Data Types

Concurrent Operations

Lab 2: Using Concurrent Statements

Processes and Variables

Lab 3: Designing a Simple Process

Day 2

Introduction to Testbenches

ISim Simulation Tool Basics

Lab 4: Simulating a Simple Design

Creating Memory

Lab 5: Building a Dual-Port Memory

Finite State Machines

Lab 6: Building a Moore Finite State Machine

Targeting Xilinx FPGAs

Lab 7: Xilinx Tool Flow

Day 3

Loops and Conditional Elaboration

Lab 8: Using Loops

Attributes

Functions and Procedures

Packages and Libraries

Lab 9: Building Your Own Package

Interacting with the Simulation

Writing a Good Testbench

Lab 10: Building a Meaningful Testbench